In this paper, by using the properties of the cyclic Hadamard matrices of order 4t, an infinite class of (4t-1)-variable 2-resilient rotation symmetric Boolean functions is constructed, and the nonlinearity of the constructed functions are also studied. To the best of our knowledge, this is the first class of direct constructions of 2-resilient rotation symmetric Boolean functions. The spirit of this method is different from the known methods depending on the solutions of an equation system proposed by Du Jiao, et al. Several situations are examined, as the direct corollaries, three classes of (4t-1)-variable 2-resilient rotation symmetric Boolean functions are proposed based on the corresponding sequences, such as m sequences, Legendre sequences, and twin primes sequences respectively.

The IEEE 802.11 standard has been extensively deployed all over the world. Many studies have been put on its performance, especially throughput. Most research focused on the analysis of saturated throughput, but non-saturated situation is more usual in practice. By extending a saturation throughput model, a concise and novel model is proposed in this paper, which can be used to analyze both saturated and non-saturated conditions. Moreover, the model can also deal with the heterogeneous condition, which allows stations to have different traffic. Different access mechanisms and packet payloads are used in simulation to validate it, and the results show that the model is accurate.

This paper introduces and uses spider monkey optimization (SMO) for synthesis sparse linear arrays, which are composed of a uniformly spaced core subarray and an extended sparse subarray. The amplitudes of all the elements and the locations of elements in the extended sparse subarray are optimized by the SMO algorithm to reduce the side lobe levels of the whole array, under a set of practical constraints. To show the efficiency of SMO, different examples are presented and solved. Simulation results of the sparse arrays designed by SMO are compared with published results to verify the effectiveness of the SMO method.

Standard neural machine translation (NMT) is on the assumption that the document-level context is independent. Most existing document-level NMT approaches are satisfied with a smattering sense of global document-level information, while this work focuses on exploiting detailed document-level context in terms of a memory network. The capacity of the memory network that detecting the most relevant part of the current sentence from memory renders a natural solution to model the rich document-level context. In this work, the proposed document-aware memory network is implemented to enhance the Transformer NMT baseline. Experiments on several tasks show that the proposed method significantly improves the NMT performance over strong Transformer baselines and other related studies.

We propose a motion detection model, which is suitable for higher speed operation than the video rate, inspired by the neuronal propagation in the hippocampus in the brain. The model detects motion of edges, which are extracted from monocular image sequences, on specified 2D maps without image matching. We introduce gating units into a CA3-CA1 model, where CA3 and CA1 are the names of hippocampal regions. We use the function of gating units to reduce mismatching for applying our model in complicated situations. We also propose a map-division method to achieve accurate detection. We have evaluated the performance of the proposed model by using artificial and real image sequences. The results show that the proposed model can run up to 1.0 ms/frame if using a resolution of 6460 units division of 320240 pixels image. The detection rate of moving edges is achieved about 99% under a complicated situation. We have also verified that the proposed model can achieve accurate detection of approaching objects at high frame rate (>100 fps), which is better than conventional models, provided we can obtain accurate positions of image features and filter out the origins of false positive results in the post-processing.

In this paper, we study partial key exposure attacks on RSA where the number of unexposed blocks of the private key is greater than or equal to one. This situation, called generalized framework of partial key exposure attack, was first shown by Sarkar [22] in 2011. Under a certain condition for the values of exposed bits, we present a new attack which needs fewer exposed bits and thus improves the result in [22]. Our work is a generalization of [28], and the approach is based on Coppersmith's method and the technique of unravelled linearization.

At FSE 2014, Grosso et al. proposed LS-designs which are a family of bitslice ciphers aiming at efficient masked implementations against side-channel analysis. They also presented two specific LS-designs, namely the non-involutive cipher Fantomas and the involutive cipher Robin. The designers claimed that the longest impossible differentials of these two ciphers only span 3 rounds. In this paper, for the two ciphers, we construct 4-round impossible differentials which are one round more than the longest impossible differentials found by the designers. Furthermore, with the 4-round impossible differentials, we propose impossible differential attacks on Fantomas and Robin reduced to 6 rounds (out of the full 12/16 rounds). Both of the attacks need 2119 chosen plaintexts and 2101.81 6-round encryptions.

As the mainstream approach in the field of machine translation, neural machine translation (NMT) has achieved great improvements on many rich-source languages, but performance of NMT for low-resource languages ae not very good yet. This paper uses data enhancement technology to construct Mongolian-Chinese pseudo parallel corpus, so as to improve the translation ability of Mongolian-Chinese translation model. Experiments show that the above methods can improve the translation ability of the translation model. Finally, a translation model trained with large-scale pseudo parallel corpus and integrated with soft context data enhancement technology is obtained, and its BLEU value is 39.3.

The time efficiency of aerial video stitching is still an open problem due to the huge amount of input frames, which usually results in prohibitive complexities in both image registration and blending. In this paper, we propose an efficient framework aiming to stitch aerial videos in real time. Reasonable distortions are allowed as a tradeoff for acceleration. Instead of searching for globally optimized solutions, we directly refine frame positions with sensor data to compensate for the accumulative error in alignment. A priority scan method is proposed to select pixels within overlapping area into the final panorama for blending, which avoids complicated operations like weighting or averaging on pixels. Experiments show that our method can generate satisfying results at very competitive speed.

MOSFETs can be used as capacitors, but its capacitance can vary by 5 to 7 times as its terminal voltage varies. To reduce the voltage dependence of the capacitance, this paper proposed two types of devices: one is called accumulation MOSFET (AMOS) and the other is formed by two conventional PMOS connected in anti-parallel. These two devices are readily available in the standard digital CMOS processes. The proposed capacitors were implemented in three different CMOS processes. The measured results show that the capacitances of both devices have less voltage dependence than a single PMOS. The voltage dependence of the AMOS capacitance can be as small as 17%. The minimum capacitance per unit area of the AMOS is 1.8 times that of the double-poly capacitor in an analog/mixed-mode CMOS process. To verify the usefulness of these two types of capacitors, they are used as compensation capacitors in a conventional two-stage amplifier. The measured results show that the amplifier compensated by the AMOS capacitor has little variation (6%) of the unity-gain frequency over the input common-mode range. Due to its smaller die area and cheaper digital process, AMOS can be used as compensation capacitor without resorting to more expensive analog process.

In this paper, we study the problem of a Boolean function can be represented as the sum of two bent functions. This problem was recently presented by N. Tokareva when studying the number of bent functions [27]. Firstly, several classes of functions, such as quadratic Boolean functions, Maiorana-MacFarland bent functions, many partial spread functions etc, are proved to be able to be represented as the sum of two bent functions. Secondly, methods to construct such functions from low dimension ones are also introduced. N. Tokareva's main hypothesis is proved for n≤6. Moreover, two hypotheses which are equivalent to N. Tokareva's main hypothesis are presented. These hypotheses may lead to new ideas or methods to solve this problem. Finally, necessary and sufficient conditions on the problem when the sum of several bent functions is again a bent function are given.

MDS transformation plays an important role in resisting against differential cryptanalysis (DC) and linear cryptanalysis (LC). Recently, M. Sajadieh, et al.[15] designed an efficient recursive diffusion layer with Feistel-like structures. Moreover, they obtained an MDS transformation which is related to a linear function and the inverse is as lightweight as itself. Based on this work, we consider one specific form of linear functions to get the diffusion layer with low XOR gates for the hardware implementation by using temporary registers. We give two criteria to reduce the construction space and obtain six new classes of lightweight MDS transformations. Some of our constructions with one bundle-based LFSRs have as low XOR gates as previous best known results. We expect that these results may supply more choices for the design of MDS transformations in the (lightweight) block cipher algorithm.

(m+k,m)-functions with good cryptographic properties when 1≤k

Because of the algebraic attacks, a high algebraic immunity is now an important criteria for Boolean functions used in stream ciphers. In 2011, X.Y. Zeng et al. proposed three constructions of balanced Boolean functions with maximum algebraic immunity, the constructions are based on univariate polynomial representation of Boolean functions. In this paper, we will improve X.Y. Zeng et al.' constructions to obtain more even-variable Boolean functions with maximum algebraic immunity. It is checked that, our new functions can have as high nonlinearity as X.Y. Zeng et al.' functions.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.

This paper describes a new approach to the scheduling problem that assigns tasks of a parallel program described as a task graph onto parallel machines. The approach handles interprocessor communication and heterogeneity, based on using both the theoretical results developed so far and a lookahead scheduling strategy. The experimental results on randomly generated task graphs demonstrate the effectiveness of this scheduling heuristic.

We analyze the defects of window-based TCP algorithm in datacenter networks and propose Rate-based Datacenter TCP (RDT) algorithm in this paper. The RDT algorithm combines rate-based congestion control technology with ECN (Explicit Congestion Notification) mechanism of DCTCP. The experiments in NS2 show that RDT has a potential to completely avoid TCP incast collapse in datacenters and inherit the low latency advantages of DCTCP.

Cow behavior monitoring is critical for understanding the current state of cow welfare and developing an effective planning strategy for pasture management, such as early detection of disease and estrus. One of the most powerful and cost-effective methods is a neural-network-based monitoring system that analyzes time series data from inertial sensors attached to cows. For this method, a significant challenge is to improve the quality and quantity of teaching data in the development of neural network models, which requires us to collect data that can cover various realistic conditions and assign labels to them. As a result, the cost of data collection is significantly high. This work proposes a data augmentation method to solve two major quality problems in the collection process of teaching data. One is the difficulty and randomicity of teaching data acquisition and the other is the sensor position changes during actual operation. The proposed method can computationally emulate different rotating states of the collar-type sensor device from the measured acceleration data. Furthermore, it generates data for actions that occur less frequently. The verification results showed significantly higher estimation performance with an average accuracy of over 98% for five main behaviors (feeding, walking, drinking, rumination, and resting) based on learning with long short-term memory (LSTM) network. Compared with the estimation performance without data augmentation, which was insufficient with a minimum of 60.48%, the recognition rate was improved by 2.52-37.05pt for various behaviors. In addition, comparison of different rotation intervals was investigated and a 30-degree increment was selected based on the accuracy performances analysis. In conclusion, the proposed data expansion method can improve the accuracy in cow behavior estimation by a neural network model. Moreover, it contributes to a significant reduction of the teaching data collection cost for machine learning and opens many opportunities for new research.

Reducing communication overhead is a key goal of program optimization for current scalable multiprocessors. A well-known approach to achieving this is to map tasks (indivisible units of computation) to processors so that communication and computation overlap as much as possible. In an earlier work, we developed a look-ahead scheduling heuristic for efficiently reducing communication overhead with the aim of decreasing the completion time of a given parallel program. In this paper, we report on an extension of the algorithm, which fills in the idle time slots created by interprocessor communication without increasing the algorithm's time complexity. The results of experiments emphasize the importance of optimally filling idle time slots in processors.